Various communication methods such as cellular communication systems typified by Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Enhanced Data for GSM Evolution; Enhanced Data for GPRS (EDGE), Wideband Code Division Multiple Access (WCDMA), Digital Cellular System (DCS), and Personal Communication System (PCS) and a wireless LAN are being developed. In recent years, a multimode/multiband transceiver as a single terminal adapted to a plurality of communication methods and transmission/reception frequency bands is in demand.
Patent document 1 described below discloses a multiband transceiver. A transmitter includes a quadrature modulator for up-converting a transmission baseband signal to an intermediate frequency transmission signal, a band pass filter, an up-converter for generating an RF transmission signal from the intermediate frequency transmission signal and an RF local signal, and a high power amplifier. The quadrature modulator includes a π/2 phase shifter to which an intermediate frequency local signal of 200 MHz from a local oscillator is supplied, two mixers to which the transmission baseband signal and two intermediate frequency local signals having a phase difference of π/2 (90 degrees) generated by the π/2 phase shifter are supplied, and an adder coupled to the two mixers. For multiband transmission, two RF local oscillators and two frequency dividers are used.
Non-patent document 1 below describes an integrated circuit (IC) for a tri-band third-generation cellular transceiver of 2100, 1900, and 850/800 MHz for worldwide use. The RF transceiver has a baseband signal processing IC for the tri-band WCDMA, and the quad band GSM/EDGE. In the non-patent document 1, the following six frequency bands proposed by 3rd Generation Partnership Project (3GPP) are described.
BandUplinkDownlinkUnitAreaBand I1920 to 19802110 to 2170MHzEuropeBand II1850 to 19101930 to 1990MHzU.S.A.Band III1710 to 17851805 to 1880MHzEuropeBand IV1710 to 17552110 to 2155MHzU.S.A.Band V824 to 849869 to 894MHzU.S.A.Band VI830 to 840875 to 885MHzJapan
The RF integrated transceiver described in the non-patent document 1 also includes a receiver to which RF reception signals of downlink frequencies of the bands III and V are supplied, a transmitter for generating RF transmission signals of the uplink frequencies of the bands III and V, and a frequency synthesizer. The frequency synthesizer includes two integrated voltage-controlled oscillators (VCO) for the receiver and the transmitter and two fractional N synthesizers. As well known, by using the fractional N synthesizers, the frequency dividing number of the frequency divider of a PLL circuit is set to not only integers but also fractions. Consequently, an oscillation frequency other than integer times of reference frequency can be obtained from output of the voltage-controlled oscillator (VCO).
The receiver includes a first reception mixer to which an RF reception signal having a downlink frequency of about 2 GHz of the bands I and II is supplied, and a second reception mixer to which an RF reception signal having the downlink frequency of about 0.9 GHz of the band V is supplied. Between a reception voltage-controlled oscillator (RxVCO) covering the frequency band of 3476 to 4340 MHz and the first and second reception mixers, a reception frequency divider capable of setting frequency dividing numbers 2 and 4 is coupled.
The transmitter includes a first transmission mixer for generating an RF transmission signal having an uplink frequency of about 1.9 GHz of the bands I and II, and a second transmission mixer for generating an RF transmission signal having an uplink frequency of about 0.8 GHz of the band V. Between a transmission voltage-controlled oscillator (TXVCO) covering the frequency band of 3296 to 3960 MHz and the first transmission mixer, a first transmission frequency divider in which the frequency dividing number is set to 2 is coupled. Between the transmission voltage-controlled oscillator (TXVCO) and the second transmission mixer, a second transmission frequency divider in which the frequency dividing number is set to 4 is coupled.
On the other hand, non-patent document 2 describes an RF front-end receiver chip to which three frequency bands of an RF reception signal of WCDMA, an RF reception signal of GSM900, and an RF reception signal of DCS1800 are supplied. The frequency of the RF reception signal of WCDMA is 2110 to 2170 MHz, the frequency of the RF reception signal of GSM900 is 925 to 960 MHz, and the frequency of the RF reception signal of DCS1800 is 1805 to 1880 MHz. The RF reception signal of WCDMA is supplied to the input of a built-in WCDMA low-noise amplifier via an external low noise amplifier (LNA) and an interstage band-pass filter of a surface acoustic wave (SAW) filter. The RF reception signal of DCS1800 and the RF reception signal of GSM900 are supplied to the input of the built-in DCS1800 low noise amplifier and the input of the built-in GSM900 low noise amplifier, respectively.
An RF reception amplified output signal of the built-in WCDMA low noise amplifier is supplied to the input terminal of one of a pair of first I, Q down-conversion mixers. An external reception local signal from a reception voltage-controlled oscillator (VCO) on the outside of the chip is supplied to a first frequency divider in which the frequency dividing number is set to 2, and a first reception local signal having a phase difference of 90° from an output of the first frequency divider is supplied to the other input terminal of the pair of first I, Q down-conversion mixers.
An RF reception amplified output signal of the built-in DCS1800 low noise amplifier is supplied to the input terminal of one of a pair of second I, Q down-conversion mixers. An external reception local signal from a reception voltage-controlled oscillator (VCO) on the outside of the chip is supplied to a second frequency divider in which the frequency dividing number is set to 2, and a second reception local signal having a phase difference of 90° from an output of the second frequency divider is supplied to the other input terminal of the pair of second I, Q down-conversion mixers.
An RF reception amplified output signal of the built-in GSM900 low noise amplifier is supplied to the input terminal of one of a pair of third I, Q down-conversion mixers. An external reception local signal from a reception voltage-controlled oscillator (VCO) on the outside of the chip is supplied to a third frequency divider in which the frequency dividing number is set to 4, and a third reception local signal having a phase difference of 90° from an output of the third frequency divider is supplied to the other input terminal of the pair of third I, Q down-conversion mixers.
The first I, Q down-conversion mixer pair for WCDMA employs a zero IF architecture whose output frequency is a baseband signal frequency. However, the second down-conversion mixer pair for DCS1800 of GSM and the second down-conversion mixer pair for GSM900 employ a low intermediate frequency (low IF) architecture whose output frequency is higher than the baseband signal frequency. As the down-conversion mixers, well-known double-balanced gilbert cell mixers are used.
As the first, second, and third frequency dividers for generating reception local signals having a phase difference of 90°, ECL-like D-type flip flops are cascaded in two or four stages. The D-type flip flop is constructed by a sampling stage and a latch stage. The sampling stage includes a first MOS transistor having a gate to which a non-inversion clock CLK is supplied and having a source coupled to the ground voltage via a current source. The latch stage includes a second MOS transistor having a gate to which an inversion clock/CLK is supplied and having a source coupled to the ground voltage via the current source. The sampling stage also includes third and fourth MOS transistors having gates to which a non-inversion input signal D and an inversion input signal /D are supplied and having sources commonly coupled to the drain of the first MOS transistor. The drains of the third and fourth MOS transistors are coupled to the power source voltage via resistors. The latch stage further includes fifth and sixth MOS transistors whose gates are coupled to the drains of the fourth and third MOS transistors in the sampling stage, and whose sources are commonly coupled to the drain of the second MOS transistor. The drain of the third MOS transistor in the sampling stage, the drain of the fifth MOS transistor in the latch stage, and the gate of the sixth MOS transistor are commonly coupled to a non-inversion output terminal Q. The drain of the fourth MOS transistor in the sampling stage, the drain of the sixth MOS transistor in the latch stage, and the gate of the fifth MOS transistor are commonly coupled to an inversion output terminal/Q. ECL stands for an emitter coupled logic as a high-speed bipolar logic circuit.
Patent document 2 described below discloses a multiband transceiver having a plurality of voltage-controlled oscillators, a transmission/reception mixer unit, and a modulator/demodulator. In the configuration, a plurality of voltage-controlled oscillators adapted to bands of different oscillation frequencies are disposed. By outputting a switching instruction according to a desired frequency band from a controller, the voltage-controlled oscillators are switched to support multiband transmission/reception.
[Non-patent Document 1]
    D. L. Kaczman et al, “A Single-Chip Tri-Band (2100, 1900, and 850/800 MHz) WCDMA/HSDPA Cellular Transceiver”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 5, May 2006, pp. 1122-1132[Non-patent Document 2]    Chun-Lin Ko et al, “A CMOS Dual-Mode RF Front-End Receiver for GSM and WCDMA”, 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuit (AP-ASIC2004), Aug. 4 and 5, 2004, pp. 374-377[Patent Document 1]    Japanese Unexamined Patent Publication No. 2002-280924[Patent Document 2]    Japanese Unexamined Patent Publication No. 2000-269848